? semiconductor components industries, llc, 2014 november, 2014 ? rev. 1 1 publication order number: nss60100dmt/d nss60100dmt 60 v, 1 a, low v ce(sat) pnp transistors on semiconductor?s e 2 poweredge family of low v ce(sat) transistors are miniature surface mount devices featuring ultra low saturation voltage (v ce(sat) ) and high current gain capability. these are designed for use in low voltage, high speed switching applications where affordable efficient energy control is important. typical applications are dc?dc converters and led lightning, power management etc. in the automotive industry they can be used in air bag deployment and in the instrument cluster. the high current gain allows e 2 poweredge devices to be driven directly from pmu?s control outputs, and the linear gain (beta) makes them ideal components in analog amplifiers. features ? nsv prefix for automotive and other applications requiring unique site and control change requirements; aec?q101 qualified and ppap capable ? NSV60100DMTWTBG ? w ettable flanks device ? these devices are pb?free, halogen free/bfr free and are rohs compliant maximum ratings (t a = 25 c) rating symbol max unit collector?emitter voltage v ceo 60 vdc collector?base voltage v cbo 60 vdc emitter?base voltage v ebo 6 vdc collector current ? continuous i c 1 a collector current ? peak i cm 2 a stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. thermal characteristics characteristic symbol max unit thermal resistance junction?to?ambient (notes 1 and 2) r ja 55 c/w total power dissipation per package @ t a = 25 c (note 2) p d 2.27 w thermal resistance junction?to?ambient (note 3) r ja 69 c/w power dissipation per transistor @ t a = 25 c (note 3) p d 1.8 w junction and storage temperature range t j , t stg ?55 to +150 c 1. per jesd51?7 with 100 mm 2 pad area and 2 oz. cu (dual operation). 2. p d per t ransistor when both are turned on is one half of total p d or 1.13 w atts. 3. per jesd51?7 with 100 mm 2 pad area and 2 oz. cu (single?operation). ap = specific device code m = date code = pb?free package ap m 1 2 3 6 5 4 wdfn6 case 506an marking diagram 1 pin connections device package shipping ? ordering information nss60100dmttbg wdfn6 (pb?free) 3000/tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specification brochure, brd8011/d. (note: microdot may be in either location) NSV60100DMTWTBG wdfn6 (pb?free) 3000/tape & reel 60 volt, 1 amp pnp low v ce(sat) transistors www. onsemi.com
nss60100dmt www. onsemi.com 2 table 1. electrical characteristics (t a = 25 c unless otherwise noted) characteristic symbol min typ max unit off characteristics collector?emitter breakdown voltage (i c = ?10 ma, i b = 0) v (br)ceo ?60 v collector?base breakdown voltage (ic = ?0.1 ma, i e = 0) v (br)cbo ?80 v emitter?base breakdown voltage (i e = ?0.1 ma, i c = 0) v (br)ebo ?6 v collector cutoff current (v cb = ?60 v, i e = 0) i cbo ?100 na emitter cutoff current (v be = ?5.0 v) i ebo ?100 na on characteristics dc current gain (note 4) (i c = ?100 ma, v ce = ?2.0 v) (i c = ?500 ma, v ce = ?2.0 v) (i c = ?1 a, v ce = ?2.0 v) (i c = ?2 a, v ce = ?2.0 v h fe 150 120 90 40 230 180 140 80 collector?emitter saturation voltage (note 4) (i c = ?500 ma, i b = ?50 ma) (i c = ?1 a, i b = ?50 ma) (i c = ?1 a, i b = ?100 ma) v ce(sat) ?0.115 ?0.250 ?0.200 ?0.160 ?0.350 ?0.300 v base emitter saturation voltage (note 4) (i c = ?500 ma, i b = ?50 ma) (i c = ?1 a, i b = ?50 ma) (i c = ?1 a, i b = ?100 ma) v be(sat) ?1.0 ?1.0 ?1.1 v base?emitter turn?on voltage (note 4) (i c = 500 ma, i b = 50 ma) v be(on) ?0.9 v dynamic characteristics output capacitance (v cb = 10 v, f = 1.0 mhz) c obo 18 pf cutoff frequency (i c = 50 ma, v ce = 2.0 v, f = 100 mhz) f t 155 mhz switching times delay time (v cc = ?10 v, i c = ?0.5 a, i b1 = ?25 ma, i b2 = 25 ma) t d 15 ns rise time (v cc = ?10 v, i c = ?0.5 a, i b1 = ?25 ma, i b2 = 25 ma) t r 13 ns storage time (v cc = ?10 v, i c = ?0.5 a, i b1 = ?25 ma, i b2 = 25 ma) t s 360 ns fall time (v cc = ?10 v, i c = ?0.5 a, i b1 = ?25 ma, i b2 = 25 ma) t f 22 ns product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. 4. pulse condition: pulse width = 300 sec, duty cycle 2%
nss60100dmt www. onsemi.com 3 typical characteristics figure 1. dc current gain figure 2. dc current gain i c , collector current (a) i c , collector current (a) 10 1 0.1 0.01 0.001 0 50 100 150 200 300 350 400 10 1 0.1 0.01 0.001 0 50 100 150 200 250 350 400 figure 3. collector current as a function of collector emitter voltage figure 4. collector?emitter saturation voltage v ce , collector emitter voltage (v) i c , collector current (a) 6 5 4 3 2 1 0 0 0.2 0.6 0.8 1.2 1.6 1.8 2.2 10 1 0.1 0.01 0.001 0.01 0.1 1 figure 5. collector?emitter saturation voltage figure 6. collector?emitter saturation voltage i c , collector current (a) i c , collector current (a) 10 1 0.1 0.01 0.001 0.01 0.1 1 1 0.1 0.01 0.001 0.01 0.1 1 h fe , dc current gain h fe , dc current gain i c , collector current (a) v ce(sat) , collector?emitter saturation (v) v ce(sat) , collector?emitter saturation (v) v ce(sat) , collector?emitter saturation (v) 250 v ce = 2 v 150 c 100 c 25 c ?55 c 300 v ce = 5 v 150 c 100 c 25 c ?55 c 0.4 1.0 1.4 2.0 i b = 20 ma 2.0 ma 4.0 ma 6.0 ma 8.0 ma 10 ma 12 ma 14 ma 16 ma 18 ma i c /i b = 20 150 c 100 c 25 c ?55 c i c /i b = 50 150 c 100 c 25 c ?55 c i c /i b = 100 150 c 100 c 25 c ?55 c
nss60100dmt www. onsemi.com 4 typical characteristics figure 7. base?emitter saturation voltage figure 8. base?emitter ?on? voltage i c , collector current (a) i c , collector current (a) 10 1 0.1 0.01 0.001 0 0.5 1.0 10 1 0.1 0.01 0.001 0 0.2 0.4 0.6 0.8 1.0 1.2 figure 9. collector saturation region figure 10. input capacitance i b , base current (a) v cb , collector?base voltage (v) 1 0.1 0.01 0.001 0.0001 0 0.1 0.3 0.4 0.5 0.7 0.9 1.0 30 25 20 15 10 5 0 0 5 15 20 30 35 45 50 figure 11. output capacitance figure 12. f t , current gain bandwidth product v eb , base?emitter voltage (v) i c , collector current (ma) 7 56 4 3 2 1 0 40 80 120 160 200 240 1000 100 10 1 1 10 100 1000 v be(sat) , base?emitter saturation (v) v be(on) , base?emitter voltage (v) v ce(sat) , collector?emitter saturation (v) c obo , output capacitance (pf) c ibo , input capacitance (pf) i c /i b = 20 150 c 100 c 25 c ?55 c v ce = 2 v 150 c 100 c 25 c ?55 c 0.2 0.6 0.8 t a = 25 c i c = 2.0 a i c = 1.0 a i c = 0.5 a i c = 0.1 a 10 25 40 t a = 25 c f = 1 mhz t a = 25 c f = 1 mhz f t , current gain bandwidth product (mhz) t j = 25 c v ce = 2 v f test = 100 mhz
nss60100dmt www. onsemi.com 5 typical characteristics figure 13. power derating temperature ( c) 150 125 100 75 50 25 0 0 0.5 1.0 1.5 2.0 2.5 p d , power dissipation (w) figure 14. thermal resistance by transistor t, pulse time (sec) 0.000001 0.1 1 10 100 r(t), effective transient thermal resistance ( c/w) 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000 single pulse 0.01 0.02 0.05 0.10 0.20 duty cycle = 0.5 figure 15. thermal resistance for both transistors t, pulse time (sec) 0.000001 0.1 1 10 100 r(t), effective transient thermal resistance ( c/w) 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000 single pulse 0.01 0.02 0.05 0.10 0.20 duty cycle = 0.5
nss60100dmt www. onsemi.com 6 package dimensions notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.15 and 0.30 mm from the terminal tip. 4. coplanarity applies to the exposed pad as well as the terminals. seating plane d e 0.10 c a3 a a1 0.10 c wdfn6 2x2, 0.65p case 506an issue f dim a min max millimeters 0.70 0.80 a1 0.00 0.05 a3 0.20 ref b 0.25 0.35 d 2.00 bsc d2 0.57 0.77 0.90 1.10 e 2.00 bsc 0.25 ref e2 e 0.65 bsc k 0.20 0.30 l 0.15 bsc f pin one reference 0.08 c 0.10 c note 4 a 0.10 c note 3 l e d2 e2 b b 3 6 6x 1 k 4 0.05 c d2 f mounting footprint bottom view soldermask defined dimensions: millimeters l1 detail a l optional constructions ?? ??? ??? --- 0.10 l1 a 0.10 cb a 0.10 cb 6x 0.47 2.30 1.10 0.77 2x 1.74 0.65 pitch 6x 0.35 1 package outline on semiconductor and are registered trademarks of semiconductor co mponents industries, llc (scillc). scillc owns the rights to a numb er of patents, trademarks, copyrights, trade secrets, and other inte llectual property. a listing of scillc?s pr oduct/patent coverage may be accessed at ww w.onsemi.com/site/pdf/patent?marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/ or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typical s? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or a uthorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or us e scillc products for any such unintended or unauthorized appli cation, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unin tended or unauthorized use, even if such claim alleges that scil lc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyrig ht laws and is not for resale in any manner. p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5817?1050 nss60100dmt/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc al sales representative
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